Anti-fuses typically comprise a dielectric layer, such as an oxide or nitride, formed between two conductive plates. The anti-fuse presents a high impedance between the conductive plates before being "blown" or programmed, and a relatively low impedance between the conductive plates after being programmed. To program the anti-fuse, a programming voltage of a sufficient magnitude is applied across the conductive plates causing a "breakdown" of the dielectric layer which results in the dielectric layer having a relatively low impedance. Anti-fuses are used in a variety of applications, including selectively enabling or disabling components on a semiconductor integrated circuit. For example, in a dynamic random access memory anti-fuses are used to enable redundant rows of memory cells which are used to replace defective rows of memory cells and thereby allow an otherwise defective memory to be utilized.
FIG. 1 illustrates the structure of a conventional anti-fuse 10 formed on a silicon substrate 12 having a particular conductivity type which, in the embodiment of FIG. 1, is p.sup.- -type. The anti-fuse 10 includes a field oxide region 14 formed in the p.sup.- -type substrate 12 in a conventional manner to provide isolation of various regions formed in the substrate. An insulation layer 16, typically a deposited silicon dioxide or TEOS layer, is formed on a surface 13 of the p.sup.- -type substrate 12 and covers the field oxide region 14 to provide insulation between the substrate 12 and other components of the anti-fuse 10. A portion of the insulation layer 16 is removed in a conventional manner, such as chemical etching, to expose an area on the surface 13 of the p.sup.- -type substrate 12. A first polysilicon layer 18 is formed to contact the surface 13 in the exposed area as shown and provides a first conductive plate of the anti-fuse 10. A dielectric layer 20, typically made of silicon nitride, is conformally formed on the first polysilicon layer 18 to provide the dielectric layer of the anti-fuse 10 which is broken down during programming of the anti-fuse. A second polysilicon layer 22 is formed to conformally cover the dielectric layer 20 and extends onto the surface of the insulation layer 16 to thereby provide a second conductive plate of the anti-fuse 10.
The anti-fuse 10 further includes regions 24-28 having a conductivity type opposite that of the p.sup.- -type substrate 12 formed in the substrate 12. In the example of FIG. 1, these regions comprise the lightly doped n.sup.- -type regions 24 and 26 and a more heavily doped n.sup.+ -type region 28. The more heavily doped n.sup.+ -type region 28 is formed to improve contact resistance (resistance occurring at a polysilicon-metal junction) between the first polysilicon layer 18 and a metal layer to be described in more detail below. Typically, the regions 24-26 are formed through conventional ion implantation before the formation of the second polysilicon layer 22. During ion implantation, the second polysilicon layers 18 and 22 act as shields to implantation and thus the n.sup.- -type regions 24 and 26, which are beneath the polysilicon layers 18 and 22, are more lightly doped than the region 28 which is not covered by the polysilicon layers 18 and 22. It should be noted that the n.sup.- -type region 24 is formed incidentally during the implantation forming the regions 26 and 28 and is not required for proper functionality of the anti-fuse 10.
An insulating layer 30, typically made of boron phosphorous silicon glass, is formed on the second polysilicon layer 22 and on areas of the substrate 12 not underneath the second polysilicon layer 22 such as the portion of the surface 13 of the substrate 12 above the n.sup.+ -type region 28. The insulating layer 30 provides a passivation cover over the anti-fuse 10 to protect the anti-fuse components from external hazards. A pair of contact holes 32 are formed in the insulating layer 30 above the n.sup.- -type region 24. The contact holes 32 extend from the upper surface of the insulating layer 30 to the upper surface of the second polysilicon layer 22. A metal layer 34 is formed in a conventional manner in the contact holes 32 and on the upper surface of the insulating layer 30 to thereby make contact with the second polysilicon layer 22 and form a first terminal of the anti-fuse 10. Similarly, a pair of contact holes 36 are formed above the n.sup.+ -type region 28 extending from the upper surface of the insulating layer 30 to the surface 13 of the substrate 12. A metal layer 38 is likewise formed in these contact holes and on the upper surface of the insulating layer 30 to thereby provide a second terminal of the anti-fuse 10. The metal layer 38 is connected to the first polysilicon layer 18 through the n.sup.- -type region 26 and n.sup.+ -type region 28 which, as previously described, lower the contact resistance between the metal layer 38 and the first polysilicon layer 18.
Typically, the contact holes 32 are formed by etching the insulating layer 30 until the upper surface of the second polysilicon layer 22 is exposed. Ideally, the etching should stop precisely at the upper surface of the second polysilicon layer 22 and not extend into or beyond the second polysilicon layer 22. Because of limited control over the etching process, as well as the second polysilicon layer 22 normally being very thin, there is a high probability that these contact holes 32 will be overetched, meaning that the contact holes extend into or beyond the second polysilicon layer 22 and thus make contact with the structures below the second polysilicon layer 22.
Two potential scenarios for overetching of the contact holes 32 are illustrated by the dashed lines 40 and 42 in FIG. 1. In a first scenario indicated by the dashed lines 40, the contact hole 32 has been etched through the second polysilicon layer 22 into and through the insulation layer 16 and into the n.sup.- -type region 24. When this occurs, programming and sensing of the anti-fuse 10 may be adversely affected in two primary ways. First, when the anti-fuse 10 is being programmed, programming voltages V.sub.PP1 and V.sub.PP2 are applied, respectively, to the metal layers 34 and 38. If the contact hole 32 has been overetched as indicated by the dashed lines 40, the programming voltage V.sub.PP1 applied to the metal layer 34 is also applied to the n.sup.- -type region 24. The pn-junction of the n.sup.- -type region 24 and the p.sup.- -type substrate 12 forms a diode 44 which is reverse biased by the application of voltage V.sub.PP1 to its cathode and a back bias voltage V.sub.bb to its anode. As known in the art, the diode 44 has a reverse breakdown voltage which, when exceeded, results in a large current flow from the cathode to the anode. The reverse breakdown voltage of the diode 44 is determined by the physical sizes and doping of the region 24 and substrate 12 and is typically on the order of 12 volts for the conventional anti-fuse 10. Typically, the programming voltage V.sub.PP1 applied to the metal layer 34 is on the order of 12.2 volts and the back bias voltage V.sub.bb applied to the substrate 12 is on the order of -0.9 volts, thus applying a voltage of approximately 13.1 volts across the diode 44 and causing breakdown of the diode 44. This breakdown of the diode 44 and the resulting current flow from the n.sup.- -type region 24 to the p.sup.- -type substrate 12 may result in an insufficient programming voltage being applied to the second polysilicon layer 22 and unreliable programming of the anti-fuse 10. The breakdown of diode 44 can often times be permanent.
In addition, permanent breakdown of the diode 44 may result in a larger than normal leakage current through the diode 44 even when no programming voltage V.sub.PP1 is applied to the metal layer 34 and the voltage on the metal layer 34 may thereby be pulled to such a level that the anti-fuse 10 may be sensed by other circuitry (not shown) on the semiconductor circuit as having been programmed when in fact it has not been programmed. FIG. 2 is a functional schematic diagram of the anti-fuse 10 as it may be connected during sensing by circuitry on the semiconductor integrated circuit containing the anti-fuse. As shown, the metal layer 38 is coupled to ground and metal layer 34 is coupled to a sense terminal SENSE which is also coupled to a supply voltage V.sub.CC through a pull-up resistor 46. The polysilicon layer 18, dielectric layer 20, and polysilicon layer 22 are indicated schematically by a structure 48. When the anti-fuse 10 has not been programmed, the voltage on metal layer 34 should be approximately V.sub.CC since the structure 48 presents a high impedance and layer 34 is thereby isolated from layer 38 and ground. Excessive leakage current through the reverse biased diode 44, however, could result in a voltage drop across the pull-up resistor 46 sufficient to cause the voltage on the sense terminal SENSE to drop below a threshold level and be sensed as being low by circuitry on the integrated circuit even when the anti-fuse 10 has not been programmed.
A second dotted line 42 in FIG. 1 indicates a second potential scenario occurring when at least one of the contact holes 32 is overetched. In this situation, the contact hole 32 has been overetched such that it extends through the n.sup.- -type region 24, which has a depth of dr, and into the substrate 12 resulting in a direct short circuit between the metal layer 34 and the substrate 12. When this type of defect occurs, programming of the anti-fuse 10 is prevented since the positive programming voltage V.sub.PP1 is shorted directly to the negative back bias voltage V.sub.bb and failure of the semiconductor circuit containing the anti-fuse 10 will most likely occur.
There is a need for an anti-fuse structure allowing reliable programming and sensing of the anti-fuse and preventing defects occurring from the overetching of contact holes during formation of the anti-fuse.